• 专利附录
  • 专利说明
  • 权利要求
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    • 专利摘要:
    The invention relates to a method for securing an integrated circuit when it is produced on a plate, said method comprising the following steps: delimiting said integrated circuit plate (1) into a first zone called standard zone (5a) and in a second zone called security zone (5b), and - creation in said security zone (5b) of a network of random connection tracks (7b) configured to interconnect a set of conducting nodes (9b) thus forming a function non-clonable physics modeled by a random electrical continuity interrogable via said set of conductive nodes by a challenge-response authentication protocol.
    公开号:FR3068150A1
    申请号:FR1755651
    申请日:2017-06-21
    公开日:2018-12-28
    发明作者:Michael May；Stefan Landis；Florian Pebay-Peyroula
    申请人:Commissariat a lEnergie Atomique CEA；Commissariat a lEnergie Atomique et aux Energies Alternatives CEA；
    IPC主号:
    专利说明:

    METHOD FOR CONSTRUCTIVELY SECURING AN INTEGRATED CIRCUIT DURING ITS IMPLEMENTATION
    DESCRIPTION
    TECHNICAL AREA
    The present invention relates to the field of securing integrated circuits, in particular constructively by non-clonable physical functions.
    PRIOR STATE OF THE ART
    Currently, counterfeiting of integrated circuits poses a major problem for manufacturers and users. To fight against this counterfeiting, we seek to find ways to discriminate between a legitimate circuit and a counterfeit circuit.
    A first solution would be to assign a unique identifier for each integrated circuit and to build a database of legitimate identifiers. This solution is not very viable because it is quite simple to emulate (or replay) a valid identifier by means of a hardware or software wart.
    A more effective solution consists in using a challenge-response mechanism which makes it possible to carry out an authentication while protecting oneself from the attack by emulation (replay). This technique is based on the use of a function to calculate the response from the challenge. The function must be unique for each integrated circuit and not clonable. Indeed, an attacker must not be able to physically recreate or clone such a function. This kind of function is called “physical nonclonable function” PUF (Physical Unclonable Function).
    There are known in the prior art integrated circuits comprising different kinds of PUFs exploiting the functional dispersions inherent in the circuits.
    A first PUF technique uses the variability induced over the signal propagation times at the limits of the electronic constraints of the circuit. A first example is an integrated circuit comprising a referee PUF consisting of inserting electrical signals at the input of a long path of combinational circuits and detecting the fastest signal. A race is established in the circuit between the different signals which propagate along different combinatorial paths and the signal which arrives first is detected by the referee. The electrical input signals define the challenge or challenge and the signal detected first defines the response.
    Another example is the ring oscillator PUF described in the document by Gassend et al. Entitled "Silicon Random Functions"; proceedings of the Computer and Communications Security Conference, Nov. 2002. This PUF is composed of several delay loops oscillating at specific frequencies and which control counters. The loops are arranged in identical ways but the inherent technological dispersions lead to loops of slightly different frequencies. Thus, the loop-controlled counters are used to generate the challenge response bits.
    A second technique of PUFs exploits instabilities at startup. For example, the SRAM memories, already present in a large majority of circuits can be used as PUFs. The basic principle is to recover the memory state at startup which is normally unique. On the same principle, the PUF can be implemented by butterfly circuits (butterfly) made from the matrices of two crossed locks where the state of the memory point at startup is undetermined. This technique is described in the document by Kumar et al. entitled "The Butterfly PUF: Protecting IP on every FPGA"; Workshop on Cryptography Hardware and Embedded Systems (CHES), Sep 2007, Vienna. In the same genre, there are also circuits with bistable rings composed of an odd number of inverters and also having an undetermined state at start-up.
    A third technique of PUFs exploits the technological dispersions of resistors in a circuit. Such a technique is described in the document by R Helinski et al. entitled "A Physical Unclonable Function Defined Using Power Distribution System Equivalent Résistance Variations"; DAC 2009. More specifically, the authors propose to measure the voltage drop in an integrated circuit between supply planes and ground planes due to technological dispersions of the resistances defined by the conductive tracks and the interconnections of the circuit. The voltage drop is proportional to the current measured in short-circuit inverters arranged over the entire surface of the circuit.
    However, all the PUFs described above are based on operations at the limits of the electronic constraints of the circuits and are therefore very sensitive to environmental variations. In particular, changes in temperature, supply voltages or electromagnetic interference can affect their performance by reducing their robustness and increasing their volatility (i.e. their intra-circuit variability). Thus, for a constant challenge, the PUF can return different results depending on the environmental conditions implying the fact that a legitimate circuit can possibly be declared as being counterfeited.
    Another problem concerns the aging of the integrated circuit. Indeed, due to operation at the limits of electronic constraints, the slightest small fault that can occur during aging of the circuit means that the PUF no longer responds in the same way and therefore, we can no longer identify the integrated circuit. .
    To overcome these faults, it is often necessary to add to the PUF a post-processing circuit of the response received which is costly in terms of footprint and consumption.
    The object of the present invention is to provide a method for securing an integrated circuit overcoming the aforementioned drawbacks, in particular by producing a PUF almost insensitive to variations in environmental conditions without the addition of an expensive post-processing circuit. and without the introduction of significant modifications in the manufacturing process of the circuit.
    STATEMENT OF THE INVENTION
    This objective is achieved with a method for securing an integrated circuit when it is produced on a plate, said method comprising the following steps:
    delimitation of said integrated circuit plate in a first zone called the standard zone and in a second zone called the safety zone, and
    -creation in said security zone of a network of random connection tracks configured to interconnect (randomly) a set of conductive nodes thus forming a non-clonable physical function modeled by a random electrical continuity interrogable via said set of conductive nodes by a challenge-response authentication protocol.
    This makes it possible to identify and secure the integrated circuit in a robust manner and insensitive to variations in environmental conditions. Unlike the prior art, this method does not use means not controlled in the electrical operation of the circuit but in the manufacturing process itself.
    Advantageously, said network of random connection tracks is created during the manufacture of the circuit by a transfer of a pattern of links produced randomly by a phase separation between at least two components of a block copolymer. Advantageously, the masks for producing the circuits are identical, the variability on the network of random tracks being inserted during manufacture.
    Thus, the method exploits uncontrolled and random means in the material production of the interconnection structure.
    Advantageously, a first subset of conductive nodes is configured to receive a challenge, while a second complementary subset of conductive nodes is configured to provide the response to said challenge.
    This allows for very secure authentication protected against replay attacks.
    According to a first embodiment, said first and second subsets of conductive nodes are formed on the same contact level.
    According to a second embodiment, said first subset of conductive nodes is formed on a first contact level while said second subset of conductive nodes is formed on a second contact level.
    According to a first preferred embodiment of the present invention, the security of the integrated circuit is integrated at the level of the implementation of a back-end of said integrated circuit and comprises the following steps:
    realization of a first level of contact on the surface of said standard and safety zones of said plate of the integrated circuit,
    depositing on the surface of said first contact level of a first multilayer comprising a barrier to metallic diffusion as well as an etching mask,
    depositing on said first multilayer at least one second layer comprising said block copolymer,
    thermal annealing of the plate generating a laminar self-organization of said block copolymer,
    -insolation of said safety zone rendering one of the two components of said block copolymer soluble,
    application of a solution suitable for removing said soluble component from said copolymer by dissolution leaving in place in said safety zone only the pattern of links formed by a single phase of said block copolymer,
    transfer of said pattern of links from said security zone into the etching mask, thus forming etchings of corresponding links,
    -cleaning the surface of standard and safety zones,
    - resumption of the usual manufacturing course to create engravings of the circuit provided in the standard area, and
    - filling of the engravings in the standard and safety zones with a conductive metal.
    Thus, the random part is in the manufacturing process and not in different masks or engravings. In addition, all of the successive stages are regulated and controlled in order to ensure extremely low variability of the key functionality parameters of the integrated circuits. In addition, because the realization of the network of random connection tracks is not controlled, the cost of cloning becomes excessively high and reverse engineering, both by imaging and by learning, is extremely difficult.
    Advantageously, the method further comprises the production of a second level of contact on the surface of the standard and safety zones.
    This makes it possible to increase the number of logic challenge-response inputs and outputs further securing the authentication protocol.
    According to a particular embodiment of the present invention, said block copolymer consists of a first homopolymer of the polystyrene type "PS" and of a second homopolymer of the poly methyl methacrylate type "PMMA".
    Thus, the two homopolymers have different physicochemical properties making it possible to separate them in a controlled manner.
    Advantageously, said at least one second layer comprises a first intermediate layer of etching mask of the “spin on carbon” type SOC and a second intermediate layer of “anti-reflective silicone coating” SiARC.
    This makes it possible to increase the transfer capacity for producing very small patterns of the order of a few tens of nanometers.
    Advantageously, the method comprises an application of a voltage greater than the reading voltage to snap fragile connection tracks.
    This eliminates fragile contacts and thus virtually eliminates any variation by aging.
    According to another embodiment of the present invention, the securing of the integrated circuit is carried out at the front end.
    The invention also relates to a secure integrated circuit which can be obtained using a method according to the invention.
    BRIEF DESCRIPTION OF THE DRAWINGS
    The present invention will be better understood on reading the description of exemplary embodiments given purely by way of non-limiting indication, with reference to the appended drawings in which:
    Fig. 1 very schematically illustrates a method for securing an integrated circuit, according to an embodiment of the invention;
    Fig. 2 very schematically illustrates a sectional view of a secure integrated circuit produced by the security method according to one embodiment of the invention;
    Figs. 3A-3K very schematically illustrate steps of a method for securing an integrated circuit, according to a preferred embodiment of the invention;
    Fig. 4A illustrates an example of a non-homogeneous layer of a block copolymer of the PS-PMMA type, according to the invention; and
    Fig. 4B illustrates links formed by a single phase of the block copolymer, according to the invention.
    DETAILED PRESENTATION OF PARTICULAR EMBODIMENTS
    The concept underlying the invention is the voluntary and random creation of a network of metallic connection links during the production of the integrated circuit by the controlled introduction of a phase separation material.
    Fig. 1 very schematically illustrates a method for securing an integrated circuit, according to an embodiment of the invention.
    The securing method according to the invention fits perfectly into the manufacturing process as such of the integrated circuit 1 on a silicon wafer 3. In the manufacturing process, the drawings on the silicon wafer 3 are created according to a photo-repetition method making each integrated circuit identical to the others. All of the successive stages are regulated and controlled in order to ensure extremely low variability in the functional parameters of the integrated circuits. However, the manufacturing method comprises steps of intrinsically random physical implementations introducing discernible characteristics which ensure the uniqueness of each integrated circuit 1 without modifying their initial functional parameters.
    Indeed, during the usual production of the integrated circuit 1 (or electronic chip), the security method includes the delimitation of the integrated circuit 1 into a first surface area called the standard area 5a and into a second surface area called the safety area 5b. The standard area 5a corresponds to the functional part of the integrated circuit 1. In fact, it is occupied by the basic electronic components adapted to perform the particular functions of the circuit. On the other hand, the security zone 5b is occupied by a non-clonable physical function PUF intended for securing the basic circuit.
    More particularly, during the manufacture of the integrated circuit, the security method includes the creation in the security zone 5b of a network of random connection tracks 7b configured to randomly interconnect a set of conductive nodes 9b. It will be noted that these conductive nodes 9b are like their equivalent conductive nodes of the standard area 5a placed in a determined and non-random manner. Furthermore, the network of random connection tracks 7b is in a plane (dotted line) which is at the same level as the plane of the conductive tracks 15a of the standard area 5a. The network of random connection tracks 7b of the security zone 5b is thus modeled by random electrical continuity which can be interrogable via the set of conductive nodes 9b by a challenge-response authentication protocol.
    Advantageously, the network of random connection tracks 7b of the safety zone 5b is created by a transfer of a pattern of links carried out randomly by a phase separation between at least two components of a copolymer with heterogeneous structure and more particularly d 'a block copolymer (see Fig. 4A). This creation of the network of random connection tracks 7b is based on self-organization (or self-arrangement) properties of the heterogeneous structure copolymer.
    Advantageously, the block copolymer used consists of a first homopolymer of the “PS” polystyrene type grafted to a second homopolymer of the “poly methyl methacrylate” (PMMA) type. The organizational scheme of the PS-PMMA block copolymer depends on the mass or molar proportion of one block relative to the other. In particular, it is known that in the case where the relative fraction of a block is around 50% by volume, it is possible to obtain a pattern composed of lines of PS interleaved in lines of PMMA. The PS-PMMA block copolymer can advantageously be used in a clean room. In fact, this block copolymer is currently used in the environment for manufacturing microelectronic components. More particularly, complex methods are used to create perfectly parallel lines from block copolymers in order to manufacture the microelectronic components. Such a method is for example described in the document Cheng et al, ACS Nano, Vol. 4, No. 8, 4815-4823, 2010 IBM Almaden Research Center. The aim of the prior art is thus to overcome the impropriety resulting from a disorder inherent in the random self-organization of block copolymers in order to control the production of straight lines.
    On the other hand, the method of the present invention non-obviously transforms the disadvantage of the prior art into an advantage by using the property of self-organization of block copolymers to create in a simple manner a network of random connection tracks allowing to model a PUF.
    According to one embodiment of the invention, after delimiting the plate of the integrated circuit 1 in a standard zone 5a and in a safety zone 5b, the surface of the plate 3 having to be structured with the block copolymer is prepared by the deposition of a so-called neutral layer. This neutral layer is prepared according to the nature of the constituents of the block copolymer. The neutral layer has the same affinity for the two components PS and PMMA, making it possible to obtain an organization perpendicular to the surface of the interlaced lines of PS and PMMA. For example, the neutral layer is a statistical copolymer of PS and PMMA (i.e. instead of having a block of PS and a block of PMMA, the two components of the statistical copolymer are linked in a random fashion).
    The block copolymer is first diluted in a solvent to form a solution having a concentration of a few percentages by mass before depositing it by centrifugation on the neutral layer of the plate 3. For example, the concentration of the solution block copolymer is between about 1% and 5% by mass. A first annealing is then carried out for a few minutes at a temperature of 10 to 30 degrees above the glass transition temperature of the block copolymer in order to facilitate the evaporation of the residual solvent in the deposited layer.
    Then, an organizational annealing is carried out to effect the phase separation between the two blocks of the copolymer. Indeed, the block copolymer compounds are organized under the effect of thermal annealing into a network of lines and spaces of period Lo, thus defining constant line and space lengths. The value of the period Lo is determined by the length of the molecular chains of the blocks making up the copolymer. This period Lo is typically between 20nm and lOOnm, which makes it possible to create lines having a length between lOnm and 50nm. For example in the case of a block copolymer of the PS-PMMA type, it is possible to obtain a period Lo of the order of 40 nm for a thickness of resin film of between approximately 30 nm and 60 nm by annealing at a temperature of the order of 200 ° C to 240 ° C for a period of 5 to 10 minutes.
    A step of insolation and development of the patterns formed by one of the two blocks is then carried out in the safety zone 5b so as to keep only a single block on its surface to be structured. This resin surface is thus obtained on this surface of the safety zone 5b which can be transferred thereafter by dry etching making it possible to create the network of random connection tracks 7b.
    Finally, a cleaning step (stripping) is carried out to clean the surface of the safety zone 5b and that of the standard zone 5a of the remaining polymer residues before resuming the usual course of manufacture of the integrated circuit 1.
    Fig. 2 very schematically illustrates a sectional view of a secure integrated circuit produced by the security method according to one embodiment of the invention.
    The secure integrated circuit (or secure electronic chip) thus comprises a standard zone 5a and a security zone 5b. The standard area 5a usually comprises at least one contact level 11a comprising conductive nodes 9a interconnecting at least two standard levels of conductive tracks 13a, 15a to the various electronic components (not shown) of the integrated circuit 1 (see also Fig. 1 ). More particularly, the example of FIG. 2 shows a first level of contact 11a (or lower level of contact) and a second level of contact 17a (or higher level of contact) in the standard area 5a.
    The security zone 5b comprises a network of random connection tracks 7b coupled to at least one contact level 11b comprising a set of conductive nodes 9b adapted to test the electrical continuity of this network of random connection tracks 7b. The example in Fig. 2 shows that the safety zone 5b comprises a level of basic conductive tracks 13b as well as a single contact level 11b comprising conductive nodes 9b connecting the links of the network of random connection tracks 7b. According to this example, the upper level 117b is a solid layer (for example SiN) comprising no conductive node. It will be noted that the security zone 5b may advantageously include a plurality of networks of random connection tracks and a plurality of corresponding contact levels, thus making it possible to increase the complexity of the PUF.
    The network (s) of random connection tracks 7b models (s) electrical continuity between the various conductive nodes 9b via which a challenge-response authentication protocol can be applied. More particularly, a first subset of conductive nodes is configured to receive a stimulus defining a challenge, while a second complementary subset of conductive nodes is configured to provide an output signal corresponding to the response to said challenge. The response is thus dependent on the electrical continuity of the network of random connection tracks 7b specific to the electronic chip 1 as well as to the challenge used. The conducting nodes 9b receiving the stimulus define a safety input of the integrated circuit 1 (more precisely, of the network of random connection tracks 7b and consequently of the PUF) while those providing the response form the safety output of the integrated circuit.
    It will be noted that in the case where there is only one level of contact, the first and second subsets of conductive nodes 9b are of course formed on the same level of contact 11b. On the other hand, when there are two contact levels 11b, 17b (see Fig. 3K), the first subset of conductive nodes can be formed on a first contact level (or lower contact level) 11b while the second subset of conductive nodes can be formed on a second contact level (or higher contact level) 17b or vice versa. As a variant, the first and second subsets of conductive nodes can invariably be formed in a complementary manner on the first and second contact levels. In all cases, the conductive nodes 9b selected to form the input or the output of the PUF are predetermined according to the specifications of the authentication protocol.
    Each integrated circuit 1 resulting from the security method thus has in its security zone 5b a network of single connection tracks 7b whose manufacturing process is random and uncontrolled and therefore excessively difficult to clone.
    After the creation of secure integrated circuits, we proceed to an “enrollment” phase which consists in building a database containing legitimate pairs of “challenge-response” for each integrated circuit 1.
    Concretely, for each integrated circuit 1, a tester randomly generates a certain number N of challenges or challenges C and addresses them to the integrated circuit 1. Each challenge C consists of a stimulus which is applied to the safety input of the integrated circuit 1 and the response R to each challenge C is recovered at the safety output of the integrated circuit 1. In fact, the PUF which defines a secret function F (embodied by the network of random connection tracks 7b) calculates the response R to each challenge C (ie R = F (C)). The tester retrieves the N responses R associated with the N challenges C and stores the N corresponding pairs of challenge-response (C, R) in a database (not shown).
    Thus, the authentication of a secure integrated circuit 1 can be tested throughout its life cycle. More particularly, a user of an integrated circuit 1 can request from the manufacturer (or from the entity which owns the database of response couples) a challenge (or a challenge-response couple). Challenge C is applied to integrated circuit 1 and the latter calculates the response to challenge C. Then, the user (or the manufacturer) compares the response generated by integrated circuit 1 with that stored in the database in order to verify the legitimacy of the integrated circuit 1. Note that for greater security, the challenge-response pair already used is then deleted from the database to avoid any replay.
    Figs. 3A-3K very schematically illustrate steps of a method for securing an integrated circuit, according to a preferred embodiment of the invention.
    In a manner known to those skilled in the art, it is considered that the manufacturing of the integrated circuit 1 on the standard area 5a has been carried out beforehand according to the usual steps of preparing an oxide layer on a substrate, transferring the design of the circuit to be reproduced using a mask, etching, doping, production of following layers, etc.
    Thus, we start with a plate 3 delimited in a safety zone 5b and a standard zone 5a in which the entire so-called “front-end” manufacturing process has been carried out, that is to say that almost the entire circuit that we are trying to secure has been manufactured.
    According to this embodiment, the securing of the integrated circuit 1 then begins at the end of the front-end and is integrated into the following stages of manufacturing of semiconductor compounds at the “back-end”, that is to say say, when making the first electrical interconnections to adequately interconnect the components with each other as well as with input-output electrodes.
    Fig. 3A very schematically illustrates a first step in the security process.
    The first step E1 (FIG. 3A) consists in producing a first level of contact 11a, 11b on the surface of the standard 5a and safety 5b areas of the plate 3 of the integrated circuit 1. This first level of contact includes interconnection holes filled with a conductor of copper, aluminum or another metal or electrically conductive material thus forming a set of conductive nodes 9a, 9b. The conductive nodes are in contact with a lower line of conductive tracks 10a, 10b (copper, aluminum or other), already made. Note that this step can be considered as an initial step carried out at the "back-end" of the manufacturing process of the integrated circuit.
    The second step E2 (FIG. 3B) consists in depositing a first multilayer 19 on the surface of the first contact level 11a, 11b. The first multilayer 19 comprises a barrier to a metallic diffusion as well as a hard etching mask. This first multilayer 19 is for example a bilayer composed of a layer of SIN having the barrier function and a layer of SiO2 having the function of etching mask.
    The third step E3 (FIG. 3C) consists in depositing at least one second layer 21 comprising the block copolymer. By way of example, a block copolymer of the PS-PMMA type is used which self-organizes in PS lines intertwined in PMMA lines.
    Advantageously, said at least one second layer 21 is a stack of layers that can be deposited by the known method of "spin coating". Thus, a first intermediate layer of SOC (spin on carbon) type etching mask is deposited, a second intermediate layer of SiARC (Silicon Anti Reflective Coating) silicone coating and the layer of block copolymer in solution according to for example a concentration between approximately 1% and 5% by mass.
    The thicknesses of these three layers can vary according to the nature of the products used as well as the dimensions of the conductive lines and tracks. They are typically of the order of 150 nm for SOC, of the order of 30 nm for SiARC and of the order of 80 nm for the copolymer with heterogeneous structure. It will be noted that the intermediate layers of etching mask and coating make it possible to produce very small patterns of the order of a few tens of nanometers.
    The fourth step E4 consists in carrying out a thermal annealing of the plate 3 generating a laminar self-organization of the copolymer with heterogeneous structure into a network of lines and spaces of predetermined period by the length of the molecular chains constituting the blocks. The energy input by thermal annealing allows the two phases to be separated. An example of a non-homogeneous layer of the PS-PMMA block copolymer is illustrated in FIG. 4A. This example illustrates in particular the laminar self-organization of the PS-PMMA block copolymer in two phases represented by light and dark chains which repel each other.
    It will also be noted that the separation between the two phases can be carried out chemically using a solvent instead of thermal annealing.
    The fifth step E5 (FIG. 3D) consists in exposing, using a conventional lithography tool 23, only the safety zone 5b in order to make one of the two components of the block copolymer soluble. Indeed, for a PS-PMMA type block copolymer, the exposure chemically modifies the PMMA blocks generating a cleavage of PMMA chains and making them soluble in an appropriate solvent such as, for example, acetic acid or isopropanol.
    The sixth step E6 (FIG. 3E) consists in applying a suitable solution for removing the soluble component from the copolymer by dissolution leaving in place in the safety zone 5b only the pattern of links 211 formed by a single phase of the copolymer. More particularly, for the PS-PMMA block copolymer, the development of the units in the solvent makes it possible to leave only the PS blocks in place. Indeed, FIG. 4B illustrates the links 211 formed by a single phase of the block copolymer. On the other hand, in the standard zone 5a, the entire layer 21 of PS-PMMA block copolymer is preserved because no insolation has been produced in this zone.
    The seventh step E7 (FIG. 3F) consists in transferring the pattern of links 211 from the security zone 5b into the etching mask thus forming engravings 25 of corresponding links. In particular, the PS lines are transferred to the etching mask (i.e. SiARC first, then SOC and then SiO2). It will be noted that the etching operation is carried out selectively in the security zone 5b, leaving the standard zone 5a protected.
    The eighth step E8 (FIG. 3G) consists in cleaning the surface of the standard zone 5a and of the security zone 5b by removing both the residual resin and the SOC / SiARC etching masks.
    In the ninth step E9 (Fig. 3H), the usual manufacturing course is resumed to create engravings of the circuit initially planned in the standard area 5a. In particular, a line level lithography 27 is produced for the standard zone 5a, followed by transfer etching in the hard mask and cleaning of the resin.
    The tenth step E10 (Fig. 31) consists in transferring the link engravings 25 from the safety zone 5b as well as the lines 27 from the standard zone 5a in the etching mask, followed by the etching of the copper barrier Si N .
    The eleventh step Eli (FIG. 3J) consists in filling the engravings of links 25 of the security zone 5b as well as the engravings of lines T1 of the standard zone 5a with a conductive metal (for example, copper or aluminum). Thus, the network of random connection tracks 7b and formed in the security zone 5b on the one hand, and a standard level of conductive tracks 15a is formed in the standard zone 5a on the other hand. The filling can be carried out selectively so as not to fill the smallest engravings of links in the security zone 5b.
    According to another embodiment, the method can comprise the production of a second level of contact on the surface of the standard 5a and safety 5b zones. It will be noted that the second level of contact can only be carried out on the standard zone 5a.
    In this case, an additional step E12 is added as illustrated in FIG. 3K. In fact, in step E12 (FIG. 3K), an upper contact level 17a, 17b is formed, comprising upper interconnection nodes 29a, 29b in the standard area 5a as well as in the safety area 5b. The integrated circuit then comprises first and second levels (or lower and upper levels) of contact comprising lower interconnection nodes 10a, 10b and upper 29a, 29b.
    Advantageously, the upper interconnection nodes 29b of the security zone
    5b are offset, for example by half a period with respect to the lower interconnection nodes 10b (i.e. from the first level of contact). This spatial offset allows the upper interconnection nodes 29b not to be at the same electrical potential as the lower interconnection nodes 10b. Furthermore, the interconnection nodes in the safety zone 5b having a dimension much smaller than those in the standard zone 5a are eliminated by an electrical treatment in order to avoid any variation by aging and to increase the reliability of the PUF. More particularly, a voltage higher than the reading voltage is applied to slam the very fine partial interconnections having too high a resistance. In addition, to test the authenticity of an integrated circuit 1, a challenge signal can be applied to it having a very low current intensity which preserves the identity of the circuit throughout its life cycle.
    The methods according to the various embodiments of the invention show that all of the successive stages are regulated and controlled in order to ensure extremely low variability of the key functionality parameters of the circuit in the standard zone 5a while allowing, by construction, a uncontrolled realization of the network of random connection tracks 7b in the security zone 5b. This reinforces the uniqueness of each electronic chip 1 allowing its identification very precisely while making cloning extremely difficult.
    0 Note that the embodiment of the security method according to Figs.
    3A3K can be transposed to the “Front End”, that is to say, during the manufacturing of logic circuits.
    权利要求:
    Claims (12)
    [1" id="c-fr-0001]
    1. Method for securing an integrated circuit when it is produced on a plate, said method comprising the following steps:
    delimitation of said integrated circuit plate (1) in a first zone called the standard zone (5a) and in a second zone called the safety zone (5b), and
    -creation in said security zone (5b) of a network of random connection tracks (7b) configured to interconnect a set of conductive nodes (9b) thus forming a non-clonable physical function modeled by a random electrical continuity interrogable via said set of conductive nodes by a challenge-response authentication protocol.
    [2" id="c-fr-0002]
    2. Method according to claim 1, characterized in that said network of random connection tracks (7b) is created by a transfer of a pattern of links produced randomly by a phase separation between at least two components of a copolymer with block.
    [3" id="c-fr-0003]
    3. Method according to claim 1 or 2, characterized in that a first subset of conductive nodes is configured to receive a challenge, while a second complementary subset of conductive nodes is configured to provide the response to said challenge.
    [4" id="c-fr-0004]
    4. Method according to claim 3, characterized in that said first and second subsets of conductive nodes (9b) are formed on the same contact level.
    [5" id="c-fr-0005]
    5. Method according to claim 3, characterized in that said first subset of conductive nodes (9b) is formed on a first level of contact while said second subset of conductive nodes (29b) is formed on a second level of contact .
    [6" id="c-fr-0006]
    6. Method according to any one of claims 2 to 5, characterized in that the securing of the integrated circuit is integrated at the level of the implementation of a back-end of said integrated circuit and comprises the following steps:
    realization of a first level of contact (10a, 10b) on the surface of said standard (5a) and safety (5b) areas of said integrated circuit plate,
    depositing on the surface of said first contact level (10a, 10b) a first multilayer (11a, 11b) comprising a barrier to a metallic diffusion as well as an etching mask,
    depositing on said first multilayer at least one second layer (21) comprising said block copolymer,
    thermal annealing of the plate generating a laminar self-organization of said block copolymer,
    -insolation of said safety zone (5b) rendering one of the two components of said block copolymer soluble,
    application of a solution suitable for removing said soluble component from said copolymer by dissolving leaving in place in said safety zone (5b) only the pattern of links (211) formed by a single phase of said block copolymer,
    transfer of said pattern of links from said security zone (5b) into the etching mask, thus forming etchings of corresponding links,
    -cleaning the surface of the standard (5a) and safety (5b) zones,
    - resumption of the usual manufacturing course to create engravings of the circuit provided in the standard area (5b), and
    -filling the engravings (25, 27) in the standard (5a) and safety (5b) zones with a conductive metal.
    [7" id="c-fr-0007]
    7. Method according to claim 6, characterized in that it further comprises the production of a second level of contact (29a, 29b) on the surface of the standard (5a) and safety (5b) areas.
    [8" id="c-fr-0008]
    8. Method according to any one of claims 2 to 7, characterized in that said block copolymer consists of a first homopolymer of the polystyrene type "PS" and of a second homopolymer of the poly methyl methacrylate type "PMMA ".
    [9" id="c-fr-0009]
    9. Method according to any one of claims 6 to 8, characterized in that said at least one second layer comprises a first intermediate layer of etching mask of the “spin on carbon” type SOC and a second intermediate layer of “coating of anti reflective silicone »SiARC.
    [10" id="c-fr-0010]
    10. Method according to any one of the preceding claims, characterized in that it comprises an application of a voltage greater than the read voltage to snap fragile connection tracks.
    15
    [11" id="c-fr-0011]
    11. Method according to any one of the preceding claims, characterized in that the security of the integrated circuit (1) is carried out at the front end.
    [12" id="c-fr-0012]
    12. Secure integrated circuit produced by the method according to any one of the preceding claims.
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    同族专利:
    公开号 | 公开日
    EP3418936A1|2018-12-26|
    US11038701B2|2021-06-15|
    FR3068150B1|2020-02-07|
    US20180375670A1|2018-12-27|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    US20140042628A1|2012-08-09|2014-02-13|International Business Machines Corporation|Structure with sub-lithographic random conductors as a physical unclonable function|
    EP2819049A1|2013-06-27|2014-12-31|Nxp B.V.|Device with capacitive security shield|
    US20150084193A1|2013-09-20|2015-03-26|International Business Machines Corporation|Embedded on-chip security|
    FR2795881B1|1999-06-30|2001-08-31|St Microelectronics Sa|CIRCUIT FOR PRODUCING A HIGH VOLTAGE PROGRAMMING OF A MEMORY|
    CN101874248B|2008-09-24|2015-04-29|松下电器产业株式会社|Recording/reproducing system, recording medium device, and recording/reproducing device|
    WO2012122994A1|2011-03-11|2012-09-20|Kreft Heinz|Off-line transfer of electronic tokens between peer-devices|
    DE102012219112A1|2012-10-19|2014-04-24|Siemens Aktiengesellschaft|Use of a PUF for checking an authentication, in particular for protection against unauthorized access to a function of an IC or control unit|
    US8977847B1|2013-03-13|2015-03-10|Emc Corporation|Distributed challenge-response authentication|
    CN105324777A|2013-07-04|2016-02-10|凸版印刷株式会社|Device and authentication system|
    US9166588B2|2014-01-20|2015-10-20|Globalfoundires Inc.|Semiconductor device including enhanced variability|
    FR3026253B1|2014-09-19|2016-12-09|Commissariat Energie Atomique|SYSTEM AND METHOD FOR SECURING AN ELECTRONIC CIRCUIT|
    US9576914B2|2015-05-08|2017-02-21|Globalfoundries Inc.|Inducing device variation for security applications|
    US10382417B2|2015-08-31|2019-08-13|Mentor Graphics Corporation|Secure protocol for chip authentication|
    US10069633B2|2016-09-30|2018-09-04|Data I/O Corporation|Unified programming environment for programmable devices|
    FR3066291A1|2017-05-10|2018-11-16|Commissariat A L'energie Atomique Et Aux Energies Alternatives|METHOD OF SECURING AN INTEGRATED CIRCUIT DURING ITS ACHIEVEMENT|US11176300B2|2018-02-03|2021-11-16|Irdeto B.V.|Systems and methods for creating individualized processing chips and assemblies|
    FR3108780A1|2020-03-30|2021-10-01|Commissariat A L'energie Atomique Et Aux Energies Alternatives|Method of making an individualization zone of an integrated circuit|
    FR3108781A1|2020-03-30|2021-10-01|Commissariat A L'energie Atomique Et Aux Energies Alternatives|Method for producing a plurality of chips on a plate, each comprising an individualization zone|
    FR3112895A1|2020-07-22|2022-01-28|Commissariat A L'energie Atomique Et Aux Energies Alternatives|Method for producing an individualization zone of an integrated circuit|
    法律状态:
    2018-12-28| PLSC| Search report ready|Effective date: 20181228 |
    2019-06-28| PLFP| Fee payment|Year of fee payment: 3 |
    2020-06-30| PLFP| Fee payment|Year of fee payment: 4 |
    2021-06-30| PLFP| Fee payment|Year of fee payment: 5 |
    优先权:
    申请号 | 申请日 | 专利标题
    FR1755651|2017-06-21|
    FR1755651A|FR3068150B1|2017-06-21|2017-06-21|METHOD FOR CONSTRUCTIVELY SECURING AN INTEGRATED CIRCUIT DURING ITS IMPLEMENTATION|FR1755651A| FR3068150B1|2017-06-21|2017-06-21|METHOD FOR CONSTRUCTIVELY SECURING AN INTEGRATED CIRCUIT DURING ITS IMPLEMENTATION|
    EP18178393.7A| EP3418936A1|2017-06-21|2018-06-19|Method for securing an integrated circuit during the production thereof using random connecting trakcs|
    US16/013,350| US11038701B2|2017-06-21|2018-06-20|Method for securing an integrated circuit during fabrication|
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